2GBps Low Power D2D Interface
Overview
Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation, standard full rail to swing, or a custom low noise pseudo-differential interface. RX cells have a weak pull-down feature.
Key Features
- Core Device: 0.9V
- I/O Device: 1.8V Standard
- Core: Uses SVT only
- BEOL: Cells currently are M8 and below
- PAD: Flipchip / die-to-die packaging only, no wire-bond option
- Cell Dimension: 50um x 24um
- VDD Core: 0.9V±10%
- Temperature: -40C to 125C
- Operational Bit Rate: 2GBps (MAX is 3.5GBps over corners)
- ESD: ESD testing of the I/Os will never occur directly, but we need sufficient to mitigate die-to-die CDM stresses and assembly issues.
Deliverables
- Verilog Models for all I/O, behavioral, and stubs.
- LEF's
- CDL netlists for DRC and LVS
- GDS
- IBIS
- Liberty TIming Models
- User Guide and Documentation
Technical Specifications
Foundry, Node
28nm
Maturity
Silicon-Proven
Availability
Immediate
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