Deskew PLL IP
Welcome to the ultimate Deskew PLL IP hub! Explore our vast directory of Deskew PLL IP
All offers in
Deskew PLL IP
Filter
Compare
358
Deskew PLL IP
from 5 vendors
(1
-
10)
-
Wide-Range Low-Area Digital PLL in TSMC 28HPM
- TSMC 28HPM
- Wide Range: 40kHz to 4 GHz
- Size: <0.0mm2
-
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Process portable
- Proven (65nm to 3nm)
- Full SCAN testable
- Core voltage supply
-
TSMC CLN7FFLVT 7nm Deskew PLL - 300MHz-1500MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
TSMC CLN20SOC 20nm Deskew PLL - 700MHz-3500MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
- Low RJ output – 0.3ps RMS for the primary 5GHz output.
- A built-in bandgap block for the generation of reference voltages/currents.
-
TSMC CLN7FF 7nm Deskew PLL - 400MHz-2000MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
TSMC CLN28HPC 28nm Deskew PLL - 175MHz-875MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
TSMC CLN28HPC 28nm Deskew PLL - 350MHz-1750MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
TSMC CLN28HPC 28nm Deskew PLL - 700MHz-3500MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
-
GF L55LPE 55nm Deskew PLL - 60MHz-300MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.