Analog Subsystems IP for TSMC
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Analog Subsystems IP
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6
Analog Subsystems IP
for TSMC
from 3 vendors
(1
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6)
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Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
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Power Management Subsystem
- Start-up time: Typ 20us
- Industry standard digital interface
- Configurable logic to control sequencing and monitoring
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Sensor Interface Subsystem
- Industry standard digital interface
- Fully integrated macro
- Standard AMBA APB interface
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Integrated Droop Response System
- Observable
- Tightly Coupled
- Process Portable
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UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller