Memory Controller & PHY IP for SMIC
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Memory Controller & PHY IP
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Memory Controller & PHY IP
for SMIC
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eMMC/SDIO/SD
- Compliant with eMMC5.1 specifications, up to 200MHz
- Support HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
- Support Enhanced Strobe in HS400
- Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
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M31 ESD I/O in TSMC 12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
- High Density Library
- Customized layout and function
- Flexible cell combination
- High ESD robustness analog cells