Compression IP for SMIC

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Compare 10 Compression IP for SMIC from 4 vendors (1 - 10)
  • Bi-Directional LVDS with LVCMOS
    • Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
    • Receiver compatible with HSCL levels for differential clock/data input
    • LVDS transmitter and receiver have independent power control
    • LVDS transmitter has adjustable output current level
    Block Diagram -- Bi-Directional LVDS with LVCMOS
  • ISDB-T1, Segment Tuner (470-860MHz UHF)
    • High Performance
    • Configurable 3/4 wire controller
    • Self calibrating and programmable filter corner frequencies
    • 8 Bit electronically tunable tracking filter
    Block Diagram -- ISDB-T1, Segment Tuner (470-860MHz UHF)
  • Wide-range LVDS Video Interface
    • Wide pixel clock range: 9MHz to 190MHz (VGA to HDTV and QXGA at 60fps) = 60Mb/s to 1.33Gb/s (proven beyond 2Gb/s) -- far exceeding range of discrete interfaces
    • Compatible with 18bit, 24bit, and 30bit balanced and unbalanced pixel data
    • 2.5V or 3.3V I/O voltage operation
    • Input levels compatible with EIA/TIA-644 LVDS, subLVDS, and larger amplitude OpenLDI standards
  • Wide-range LVDS Video Interface
    • Wide pixel clock range: 9MHz to 190MHz (VGA to HDTV and QXGA at 60fps) = 60Mb/s to 1.33Gb/s (proven beyond 2Gb/s)
    • Compatible with 18bit, 24bit, and 30bit balanced and unbalanced pixel data
    • 2.5V or 3.3V I/O voltage operation
    • Programmable output levels compatible with EIA/TIA-644 LVDS, subLVDS, and larger amplitude OpenLDI standards
  • FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
    • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
    • 3.3V/1.8V 10% supply voltage, 0/+125C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 3.15Gbps bandwidth (8 to 90Mhz pixel clock for 1 channel)
  • Triple HD-video AFE digitizer - 10bits/170Mhz - 8bits/205Mhz
    • Triple channel video 10bits digitizer 170Mhz
    • 0.5 to 1V analog input range
    • 3.3V/1.8V ±10% supply voltage, -40/+125°C
    • 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
  • Triple DAC 10-Bits, voltage output - 10Mhz, 3.3V/1.3V full-scale
    • Programmable full scale : 3V or 1V.
    • 10 Bits resolution.
    • 10MS/s update rate.
    • Adjustable max output current 24, 30 or 36mA.
  • Triple Video DAC 10-Bits, 240Mhz
    • 10-Bits Resolution
    • 240MS/s Update Rate
    • 3.3V ±10% supply voltage, -40/+125°C temperature.
    • 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
  • Audio PLL - Fractional-N ±0.05 ppm accuracy
    • Fractional-N PLL : ± 0.05 ppm accuracy
    • Eliminates VCXO/DCXO requirements
    • 10-40 Mhz input
    • Audio clock supports 256*fs & 384*fs
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