Audio PLL - Fractional-N ±0.05 ppm accuracy

Overview

This PLL can generate all the frequencies used by audio systems from a stable clock of 10 to 40Mhz.
Audio clock is 256*fs0 or 384*fs1, where fs0 is 192kHz or 176.4kHz and fs1 is 96kHz or 88.2Khz.
An output divider by N generates multiple of 192kHz, 176.4kHz, 96kHz, 88.2kHz, 48kHz, 44.1kHz, 32kHz, 24kHz, 22.050kHz, 16kHz, 12kHz, 11.025kHz, and 8kHz frequencies.
An external reference current is required, and can be provided either by V-Trans Irefgen (resistor-less design +/-5%) or Refgen (with external reference resistor +/- 1%) libraries or any other third party IP.

Key Features

Fractional-N PLL : ± 0.05 ppm accuracy
Eliminates VCXO/DCXO requirements
10-40 Mhz input
Audio clock supports 256*fs & 384*fs
3.3V/1.8V ±10% supply voltage, -40/+125°C
1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
Small cell area with integrated loop filter: [contact us]
Low jitter : [contact us ]
50% duty cycle output.
Antenna diodes on each digital input.
Silicon proven.

Deliverables

Design Kit includes:

LEF view and abstract gdsII
Verilog HDL behavioral model
Liberty (.lib) timing constraints for typical, worse and best corner case
Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Tapeout kit includes the design kit plus plysical view:

gdsII
LVS netlist and report
DRC/ERC/ESD/ANT report

Technical Specifications

Maturity

silicon proven

Availability

now

GLOBALFOUNDRIES

Pre-Silicon: 180nm

SMIC

Pre-Silicon: 180nm G

Silterra

Pre-Silicon: 180nm

TSMC

Pre-Silicon: 180nm G
Silicon Proven: 180nm G

UMC

Pre-Silicon: 180nm

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Audio PLL - Fractional-N ±0.05 ppm accuracy

Overview

Key Features

Deliverables

Technical Specifications

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