The Silicon Creations 4-lane 1.0Gbps to 3.125Gbps Multi-Rate Serializer/Deserializer) macro includes all high-speed analog functions for 1 to 4 lanes of bi-directional data transport between chips over FR4 and similar PCBs and backplanes. The SerDes is optimized for low power operation with highly programmable line driver and line receiver. 20b input and output datapaths simplify design of link layers created from RTL using regular standard cells and regular synthesis, place, and route ows. Built-in BIST blocks enable stand-alone at-speed self-testing. Excellent supply noise immunity in the CDR and TX PLLs makes the SerDes ideal for use in noisy mixed signal SoC environments.
XAUI Transciever
Overview
Key Features
- Chip-chip/backplane SerDes with 4 lanes each with data rates of 1.0Gbps to 3.125Gbps
- Compatible with XAUI and custom back-planes
- Deemphasis control for line driver compensates for PCB/backplane losses
- Shared bias and TXPLL common blocks saves die area and power
- Separate Serializer and Deserializer macros simplify assembly of SerDes con gurations on single chips or separate chips
- 20-bit core interface for easy SP&R of Link Layer
- Rich testability features including digital test bus and built-in PRBS generation and detection for stand-alone at-speed testing
- P-S-S-P-G-S-S-G IO plan assures a narrow footprint to minimizes IOring requirements without sacri cing signal integrity
- IOcells and breakers included for ESD-safe drop-in integration in IOring
- Integrated BIST
- Optional external reference clock input
- Optional Frac-N operation for jitter cleaning or spread spectrum transmission
Deliverables
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note with integration and production test guidelines
Technical Specifications
Foundry, Node
TSMC 65LP
Maturity
Silicon Proven
Availability
Available Now
TSMC
Silicon Proven:
65nm
LP