VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V ANALOGIO_DUP_05 IO Library
Overview
VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18¦Ìm Logic 1P6M Salicide 1.8/3.3V process. This library provides 5V analog IO pads. This library supports Device Under Pad (DUP).
Key Features
- SMIC 0.18¦Ìm Logic 1P6M Salicide 1.8/3.3V process
- Provides 5V analog IO pads
- Supports Device Under Pad (DUP)
- Provides cells to interface with Generic IO library
- Suitable for four, five, or six metal layers of physical design
Deliverables
- Databook in electronic form
- Verilog models and Synopsys synthesis models
- Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.18um
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL
Related IPs
- VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library
- VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
- VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V VPPIO_DUP_01 IO Library
- VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO Library
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- I/O LIbrary