VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library

Overview

Key Features

• SMIC 0.13¦Ìm Logic 1P8M Salicide 1.2/3.3V process
• Provides 5V analog IO pads
• Supports Device Under Pad (DUP)
• Provides cells to interface with Generic IO library
• Suitable for six, seven, or eight metal layers of physical design
• More details, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/cn/contactus.asp

Benefits

• Databook in electronic form
• Verilog models and Synopsys synthesis models
• Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications