IP Catalog > Interface IP > Interconnect IP > USB IP > USB IP > USB Phy IP > USB3.2 PHY

USB3.2 PHY

Overview

The Innosilicon USB3.2 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for USB3.2 standard from Intel. The PHY supports USB3.2 SuperSpeed physical layer specifications.

Streamlined production testing is supported through BIST, multiple loopback modes and boundary scan. Its modular nature is flexible, ensuring a PHY combination that is able to support the latest in C-type connector configurations while including all the I/Os, ESD in a single drop-in block. As with all Innosilicon IP, our USB 3.2 solution is fully customizable to meet your specific needs.

Key Features

  • Reference Clock:
    • 25-300MHz, integer multiple of Serial output
    • +/-300ppm frequency stability (<20Gbps)
    • Support both SRNS & SRIS mode
    • Configurable as reference clock repeater
  • Internal PLL:
    • Used to drive all PHY transmitters and receivers
    • Ring PLL covering 1.0-5Gbps
    • Programmable pre-divider & feedback divider
    • Initiative SSC or reference clock based passive SSC
    • LOCK indication
  • Data Transmit:
    • Rates supported from 1.0-5 Gbps
    • AC coupled
    • 50? impedance, internally calibrated
    • 200-1100mV differential peak-peak, programmable
    • 3 tap pre/post-cursor de-emphasis, programmable
    • Programmable Rise/Fall times
  • Data Receive:
    • AC coupled
    • 50? impedance, internally calibrated
    • 200-1200mV differential peak-peak
    • CTLE, programmable
    • DFE, 6-tap programmable
    • CDR
  • Testing:
    • Scan
    • BIST with PRBS7/23 and PRBS31 (generator & checker)
    • Loopback (near end, far end, on/off-die)
    • On-chip scope (eye height & width)
    • Analog and digital probe points
    • HTOL
    • IDDQ
  • ESD:
    • HBM 2000V, [JEDEC JS-001-2014]
    • MM 100V, [JEDEC JESD22-A115C]
    • CDM 250V, [JEDEC JESD22-C101F]
  • Latch Up:
    • +-200mA for IO and 1.5*Vsupply for power rails
  • Package:
    • Wire bond with careful SI/PI analysis for 8Gbps and below
    • Flip-Chip with careful SI/PI analysis for 8Gbps and Up
  • Interface with controller:
    • PIPE4.3 & 32 bits data bus for USB3.x

Deliverables

  • Verilog Sim Behavioral simulation model for the PHY
  • Encrypted IO spice netlist for SI evaluation
  • Integration Guidelines
  • Test Guidelines
  • GDSII Layout and layer map for foundry merge
  • Place and Route LIB and LEF views for the AFE
  • LVS and DRC verification reports

Technical Specifications

Foundry, Node
TSMC 55/40/28/22/12/3nm, Samsung 14/10/8nm, GF 55/28/22/14/12nm, SMIC 55/40/28/14nm, UMC 55/40/28/22nm, HLMC 40/28nm
GLOBALFOUNDRIES
In Production: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Samsung
In Production: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm
TSMC
In Production: 3nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 3nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
UMC
In Production: 22nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm , 55nm
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