USB 2.0 DRD Controller
Overview
Innosilicon USB2.0 DRD Controller provides a USB2.0-compliant host/device controller solution. This controller can be programmed to support data transfers at high-speed, full-speed and low-speed mode over USB protocol. The Controller IP is well designed to provide flexibility for easy and reliable integration into System-on-Chips (SoCs), and to enable seamless connectivity with an Innosilicon, or third-party, UTMI-compliant PHY. It connects the USB PHY via an 8- or 16-bit UTMI+ interface and accommodates AHB interfaces for configuration and AXI interfaces for data access. When working as a device, it supports only one port; while as a host, it supports up to 4 USB ports.
Key Features
- Compliant with xHCI specification 1.2 defined for USB host controllers
- Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
- Compliant with AMBA? AHB Protocol Specification.
- Compliant with AMBA? AXI Protocol Specification.
- Compliant with USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Specification.
- Supports various operation modes including: High-Speed (HS, 480Mbps), Full-Speed (FS, 12Mbps), and Low-Speed (LS, 1.5Mbps).
- Supports all USB transaction types including Control, Bulk, Interrupt and Isochronous transfers.
- Embedded DMA.
- UMI+ interface data bus width: 8 bits or 16 bits.
- AHB interface:
- Data Bus width: 32 bits
- Address Bus width: 32 bits
- AXI interface:
- Data Bus width: 64 bits
- Address Bus width: 64 bits
- Up to 4 downstream ports when working as a host
- Supports SCAN mode
- Optimized for low power consumption
Deliverables
- Databook
- Integration Guidelines
- Frontend simulation environment and reports/Guidelines
- Obfuscated RTL
- If customers expect us to provide Backend and Layout service, the following additional deliverables will be included:
- Post-simulation model
- Encrypted IO spice netlist for SI evaluation
- GDSII Layout and layer map for foundry merge
- Place and Route LIB and LEF views for the AFE
- LVS and DRC verification reports
Technical Specifications
TSMC
In Production:
5nm
,
12nm
Silicon Proven: 5nm , 12nm
Silicon Proven: 5nm , 12nm
Related IPs
- SuperSpeed USB 3.1 DRD Controller
- USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
- USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
- USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
- MCU-less USB Billboard Device Controller
- SuperSpeed USB 3.1 Device Controller