USB 1.x Device IP

Overview

Key Features

• Compliant with USB 1.1 specification.
• Supports UTMI and ULPI transceivers.
• Support any combinations of USB 1.1 interface speeds – LS(1.5 Mbps), FS (12.0 Mbps).
• Supports Interrupt/Bulk/Isochronous/Control Transfers.
• CRC16 checking and generation for FS/LS data packets.
• CRC5 generation and checking for Tokens.
• Supports preamble for LS transfers while operating in Host Mode.
• Supports Protocol Layer Error Handling.
• Provides prioritized scheduling for periodic endpoints.
• Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• Supports USB Suspend state and supports remote wakeup devices.
• Supports all FS USB Link Power Management States – L1, L2.
• Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
• Support for clock gating and multi-power-well support
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The USB1.x Device interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications