SPIStack Verification IP

Overview

SPIStack is the serial synchronous communication protocol based Flash VIP, supporting all major SPIStack vendors. SPIStack Verification IP can be used to verify SPIStack Master or Slave in SOC. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPIStack Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPIStack Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 100% of SPIStack protocol Standards.
Supports SPIStack devices like W25M512JV, W25Q256JV from all leading vendors like WINBOND.
Supports all SPI Transfers as per the Specification.
Supports the following SPI modes
- Standard SPI
- Dual SPI mode
- Quad SPI mode
Supports 3 or 4-Byte Addressing Mode.
Supports Software Die Select (C2h).
Supports Software and Hardware Reset
Supports Independent single die access
Supports Read while Program/Erase
Supports Multi Die Program/Erase
Supports Uniform Sector/Block Erase (4K/32K/64K-Byte)
Supports Program/Erase Suspend and Resume.
Supports Advanced Security Features
- Supports Power Supply Lock-Down and OTP protection
- Supports Top/Bottom, Complement array protection
- Supports Individual Block/Sector array protection
- Supports 3 x 256-Byte Security Registers with OTP locks
Supports 64-bit Unique ID for individual die
Supports Discoverable Parameters (SFDP) Register
Supports Volatile & Non-volatile Status Register Bits
Supports backdoor access for memory and registers
Built in functional coverage analysis.
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPIStack bus.
SPIStack Slave can be configured as standard device or can use FIFO for data passing.
Master contains rich set of commands for both standard device and FIFO model mode.
Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
SPIStack Verification IP comes with complete test suite to test every feature of SPIStack specification.

Benefits

Faster testbench development and more complete verification of SPIStack designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment

Block Diagram

Deliverables

Complete regression suite containing all the SPIStack testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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