The 10/100/1G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1000M Ethernet interface MII/SMII/RMII/GMII/RGMII. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
MII/SMII/RMII/GMII/RGMII Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MII/SMII/RMII/GMII/RGMII Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
