Power-On-Reset TSMC
Overview
The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
Key Features
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
- Current Consumption: typ 100nA
- Customizable design for simple SoC integration
- Silicon Area – Please contact Agile Analog
Benefits
- Hysteresis
- - Avoids false resets due to noisy environments
- Configurable thresholds
- - Both upper and lower thresholds are programmable
- - Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions
Block Diagram
Applications
- Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
TSMC
Maturity
Available on request
Availability
Now
TSMC
Pre-Silicon:
3nm
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4nm
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5nm
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6nm
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7nm
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10nm
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12nm
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16nm
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20nm
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22nm
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28nm
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28nm
HP
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28nm
HPC
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28nm
HPCP
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28nm
HPL
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28nm
HPM
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28nm
LP
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40nm
G
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40nm
LP
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45nm
GS
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45nm
LP
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55nm
FL
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55nm
G
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55nm
GP
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55nm
LP
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55nm
NF
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55nm
ULP
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55nm
ULPEF
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55nm
UP
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65nm
G
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65nm
GP
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65nm
LP
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80nm
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80nm
GT
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80nm
HS
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85nm
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90nm
FS
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90nm
FT
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90nm
G
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90nm
GOD
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90nm
GT
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90nm
LP
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90nm
zzz
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110nm
G
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110nm
HV
,
110nm
LVP
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130nm
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130nm
BCD
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130nm
BCD+
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130nm
G
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130nm
LP
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130nm
LV
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130nm
LVOD
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150nm
G
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150nm
LV
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160nm
G
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160nm
LP
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180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
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180nm
LP
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180nm
LV
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180nm
ULL