PCI Master/Target Interface Core

Key Features

• Flexible synthesizable HDL
• PCI specification 2.2 compliant
• 33 MHz performance
• 32-bit datapath
• Zero wait states burst mode
• Full bus Master/Target functionality
• Single interrupt support
• Type 0 Configuration space
• Support of all Base Address Registers
• Support of backend initiated target retry, disconnect and abort
• Parity generation and parity error detection.
• Available in synthesizable HDL source code
• DMA Controller Core supporting independent write and read operations available

Benefits

• Supports 32-bit address/data bus and operates up to 33 MHz (PCI clock frequency).
• Fully compliant with the PCI Local Bus Specification, Revision 2.2.
• Interface has both Master and Target capabilities.
• interface implements 64 bytes of PCI Configuration Space registers.
• is possible to extend the Configuration Space up to 256 bytes if required.
• Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB.
• Both Target and Master supported commands are:
• Configuration Read, Configuration Write
• Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL)
• I/O Read, I/O Write
• Is designed for reuse in ASIC or FPGA implementations

Deliverables

• HDL Source License
• HDL RTL source code for PCI-M32
• HDL RTL source code for DMA Controller
• Testbench
• Vectors and expected results
• Simulation & synthesis scripts
• Documentation
• Netlist License
• Post-synthesis EDIF netlist for PCI-M32
• Post-synthesis EDIF netlist for DMA Controller
• Testbench
• Vectors and expected results
• Place & Route Scripts
• Documentation

Technical Specifications