MIPI DPHY RX

Overview

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. The primary application is for the physical layer CSI-2 (Camera Serial Interface). Other applications that require a high data rate serial link may also benefit from the implementation of the D-PHY. The D-PHY implementation for CSI will provide 1 clock and 4 data lanes operating at a maximum high speed bit rate of 1600Mbps per data channel. The 4 data lanes also support low power data communication operating at a maximum bit rate of 10Mbps.

Key Features

D-PHY v1.2 compliant system interface;
Up to 4 data lanes at 80~1600Mbps per each lane;
Flexible configuration clock: 25 MHz (nominal);
Maximum LP data rate supported of 10Mbps;
LP TX available for data lane 0 and Contention Detectors;

Support bidirectional for Escape modes and Turnaround;

Low-power Escape modes and ultra-low power state (ULPS);
PHY-Protocol Interface (PPI) for clock and data lanes;
HS RX Automatic de-skew calibration;
HS RX Automatic offset calibration;
HS RX Equalizer;

Benefits

Support polarity inversion;
Resistance calibration by external reference resistor;
TSMC CRN22ULL Process;
Power Supply:

1.8V Power Supply for IO and analog;
0.9V core digital (external chip-level regulated).

Applications

Video Transmission System
Camera Sensor

Deliverables

GDSII&CDL Netlist
Verilog Model
LEF Layout Abstract(.LEF)
Liberty Timing Models(.lib)
Verify Results
Specification
Datasheet
Integration Guideline
Evaluation Plan
Leading support for package design, SI&PI modeling and production test development

Technical Specifications

Foundry, Node

28/22/14nm

Maturity

Developing

Availability

Available

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