MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane

Overview

Key Features

• MIPI DPHY v1-1 / MIPI CSI2 compliant
• Differential signal of almost CIS serial outputs support
  • 1) sub-LVDS (Maximum 1.0Gbps)
  • 2) MIPI-DPHY (Maximum 1.5Gbps)
• Input Clock Frequency:
• (sub-LVDS mode Clock Generator Input) SCK=~1000MHz
• (MIPI-DPHY mode Clock Generator Input) SCK=~1500MHz
• (sub-LVDS 8/10/12/14/16 bit SER) PCK_N= ~100MHz
• (MIPI-DPHY 8bit SER) PCK_N= ~313MHz
• Output Clock Frequency: ~750MHz Output Data Rate: ~1.5Gbps
• Power Supply : 1.8V( I/O, Analog) 1.1V(Core)
• Max TX Lane Number: Clock 1-port / Data 4 -ports (lanes)
• Data Input Path:
  • 1) MIPI DPHY (8bit Parallel)
  • 2) Others (8, 10, 12, 14, 16 bit Parallel)
• Include Power Down Mode
• Output impedance Adjustable in settings
• Process TSMC 40LP
• Various process porting support available ( Please contact us. )
• Supporting Link-layer (Soft Macro): CD12661IP

Benefits

• We are IP design professional engineering company, so we can provide the high quality and good performance solution. Also we can provide not only single-interface PHY but also multi-interface PHY.
• We are making the PHY to meet customer specification by having our own IP data base resource. Our business is very flexibility IP license model, and then we have a lot of license to many sensor companies.
• Our products can contribute to your business.

Applications

• Camera Application
  • Security Camera
  • Mobile-Phone Camera
  • DSC(Digital Still Camera)
  • Medical Camera
  • SLR
  • 3D Camera
  • Camcorder
• ISP(Image Signal Processer)

Deliverables

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX or RX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP(CD12661IP) and FPGA Board(Option)

Technical Specifications