LPDDR2/3/4/4x IP combo solution with high performance and low power

Overview

Key Features

• Support LPDDR2/LPDDR3/LPDDR4/LPDDR4x
• Support LPDDR4/4x up to 4266Mbps
• Support Multiport AMBA AXI2.0 interface, port number, asynchronous or synchronous AXI port, data width, FIFO depth, and command queue depth configurable
• Support DFI4.0 compliant interface between controller and PHY
• Support 2 ranks, max density up to 8GB
• Support automatic temperature monitor and refresh rate adjust
• Support CA, write, read VREF eye training and per-bit de-skew training, write leveling training
• Support Inline BIST and SIPI/LFSR/USER patterns
• Support DDPHY loopback test
• Support fully pin-mux easy for PKG/PCB routing
• Support mask write, write/read DBI

Benefits

• High efficiency Command Queue scheduler to provide maximum bandwidth
• Low latency, DFI PIPE configurable on both controller and PHY sides, AXI async/sync configurable, DFI ratio adjustable with frequency
• Complex QoS, high urgent, priority-based Round-robin port arbitration, timeout, bandwidth restriction supported
• Support AXI read out of order
• Support dual channel access with independent dual command queue, interleaving processed in controller; (LPDDR4)
• Support per-bank refresh and burst refresh to improve DRAM efficiency(LPDDR4)
• Support automatic clock gate, and different levels of low power mode
• (1)Doze sleep, automatic power down or self-refresh, controller clock could be closed
• (2)Light sleep, hand shake with SOC, root clock could be closed
• (3)Deep sleep, root clock could be closed and power down, data retention supported in DDRIO
• Support hardware-based DDR frequency switch (DFS), and DFI 1:2/1:1 adjustable with frequency, to reduce latency in low frequency
• Support different power mode in different rank
• Support FSP (Frequency-Set-Point) to change working frequency quickly (LPDDR4)

Applications

• PC
• Server
• Workstations
• Cell Phone
• Storage Devices

Deliverables

• Datasheet (Including Integration Guideline, Interface PINs, clock and reset description, all training flows etc.) (DDRMC & DDRPHY)
• Register Map files (register address and function description), timing calculation sheet (DDRMC & DDRPHY)
• Timing lib/db, Layout Frame (.LEF) (DDRPHY)
• Encrypted RTL and Netlist, SPEF/SDF (DDRPHY)
• Top Level GDS (DDRPHY)
• RTL Code & SDC Constraints (DDRMC)
• Verification environment and cases (testbench, DDRIO Verilog model, ddr3/ddr4 initial flow, training flow, bandwidth access, DFT pattern etc. (DDRMC & DDRPHY)

Technical Specifications