Low Power Multi-Rate SerDes

Overview

Includes all high-speed analog functions for serializer and deserializer PMA. Optimized for low power operation at target data rates. Alternative 10b and 40b input and output datapaths simplify design of link layers created from RTL using regular standard cells and regular synthesis, place and route flows. Excellent supply noise immunity in the CDR and TX PLLs makes the SerDes ideal for use in noisy mixed signal SoC environments.

Key Features

IP available with...
Data rates of <200Mb/s to >8Gb/s
Compatible with SGMII, FibreChannel, JESD 204, V-by-One
Separate PLLs for Tx and Rx support a single reference clock or separate references from 20MHz to 400MHz
Separate Serializer and Deserializer macros simplify assembly of arbitrary single- or multi-lane configurations
10bit and 40bit datapaths for easy SP&R of link layer
Flexible driver and receiver circuits compatible with LVDS and CML standards with programmable low power settings
IO library integrated to simplify integration and lower ESD risk
Trimmable on-die termination ensures excellent signal integrity
High-speed loop-back path simplifies production testing
Comprehensive power-down control

Block Diagram

Deliverables

GDSII
CDL Netlist (MG Calibre Compatible)
Functional Verilog Model
Liberty timing models (.lib)
LEF
Application Note with integration and production test guidelines

Technical Specifications

Foundry, Node

TSMC 65nm - 180nm; Global Foundries 28nm - 65nm; SMIC 65nm; Renesas 90nm

Maturity

Silicon Proven

Availability

Available Now

GLOBALFOUNDRIES

In Production: 65nm LPe
Silicon Proven: 28nm SLP

Renesas

In Production: 90nm

SMIC

Pre-Silicon: 40nm LL , 65nm LL , 90nm LL
Silicon Proven: 55nm LL

TSMC

In Production: 65nm LP
Pre-Silicon: 40nm LP , 90nm G
Silicon Proven: 180nm G

UMC

Pre-Silicon: 65nm SP

Request Info