I2C Slave To AXI Bridge IP

Overview

Key Features

• Compliant with I2C version 6.0 specification
• Full I2C Slave Functionality
• Converts I2C Transactions into AXI write or read instructions
• Allows external devices to access the internal AXI Bus
• Useful for updating device software from and external device
• Useful for reading internal memory mapped registers and memory
• Supports Mailbox Read/Write functionality
• Supports AXI Master Read/ Write capability
• Supports AXI Slave
• Supports monitoring of erroneous AXI transfers and reports error to the system
• Supports Start, Repeated start and Stop for all possible transfers
• Supports 7bit/10bit Addressing
• Supports following speed modes
• -> Standard mode
• -> Fast mode
• -> Fast plus mode
• -> High speed mode
• Supports General call address handling
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The I2C Slave To AXI Bridge interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications