High Accuracy Low Latency Sigma-Delta ADC

Overview

The AXIOM_LLSDADC1024fs is a high-resolution sigma-delta analog-to-digital converter. The latency is only one effective data output period (40ns at fCLK=50MHz), which makes the converter ideally suited for application in closed-loop digital control systems. The low latency is enabled by feedback of the bit stream output into a DAC with built-in filtering. This results in a “tracking ADC behavior”, where the output accurately tracks the input signal within the signal bandwidth. The filtering DAC makes the system robust against jitter and other error sources typically associated with 1-bit converters.

Key Features

  • Dynamic range: >114 dB (20 - 20kHz)
  • Excellent THD performance: THD < -100 dBFS
  • Integrated reference variants:
    • low noise: >106dB SINAD
    • high substrate rejection: 90dB SINAD
  • Low out-of-band-noise (OOBN): -40 dBFS
  • Robust against clock jitter
  • Multi-bit advantages with a single bit modulator
  • Full-scale differential input bandwidth: 60kHz
  • VI conversion through user specific resistance
  • Wide input common mode range
    • true ground
    • high voltage (>>VDDA)
  • Power: 30mW per channel

Benefits

  • The AXIOM_LLSDADC1024fs has an extremely low latency in combination with a high dynamic range. This makes it very suitable as feedback ADC in high performance amplifiers. The converter is able to convert both single-ended and differential signals with high accuracy. The user specific VI conversion resistances enable a wide common and differential input voltage range, which could be well outside the supply level.

Block Diagram

High Accuracy Low Latency Sigma-Delta ADC Block Diagram

Applications

  • High-quality audio ADC & DAC (codec)
  • Fully digital closed loop amplifier
  • High-precision control systems
  • Process and servo control
  • Active noise reduction systems

Deliverables

  • Behavioral model (VHDL/Verilog/Simulink)
  • Netlist (CDL)
  • Layout (GDS2)
  • Abstract (LEF)
  • Checks (DRC/LVS/ANT)
  • RTL (VHDL)
  • Timing & interface (SDC & LIB)
  • Design documentation (PDF)
  • Integration documentation (PDF)

Technical Specifications

Foundry, Node
140nm CMOS
Maturity
The design is silicon proven
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Semiconductor IP