HEVC/H.265, H.264 Multi format Dual-core Codec IP for 8K 60fps

Overview

WAVE541C is a dual-CORE codec IP, optimally architected for real-time encoding or decoding video at 8K60 in HEVC/H.265 and AVC/H.264 video formats. This IP core provides high-performance encoding and decoding capability up to 4K@120fps, 8K@60fps with a dual-core architecture and an optimized silicon area for 4K Ultra-HD applications.

SoCs powered with WAVE541C will bring 8K content readiness to video generating devices such as action cams, mobile video recorders, 360 VR devices, and many more. This readiness will enable content creators to generate videos and share them on video platforms like YouTube, which already supports 8K video streaming.

In terms of quality, considering real-time encoding at such high resolution and frame rate on portable devices, the best possible video quality is being achieved, and in terms of class competition, WAVE541C IP is designed to compete with x.264/x.265 medium preset on PC or Server.
WAVE541C: Dual-core HEVC/H.265 & AVC/H.264 combined codec IP; Encode and Decode capability of 8Kp60 content at 1GHz using 12nm or higher technology

Key Features

Video Codec Standard

HEVC: Main/Main 10 profile @ L5.1 High tier
AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2

Performance

8K60fps with a dual-core
Max resolution: 8192 x 4096
Min resolution: 720 x 128
Bit depth: 8-/10-bit depth

Features

Frame buffer compression (CFrame)
Scalable HW Architecture
Handling multi-instances
Low delay encoding/decoding
Latency tolerance
Programmability
Low power consumption
Frame-based processing
AIR for error resilience
WPP encoding with a single slice
Multi-slice
3DNR

Benefits

Burst-write-back (BWB)
Down-scaler (By on-the-fly mode)
Map converter
MPEG-2/4 De-ringing
Built-in de-blocking filter for MPEG 2/4 and DivX
Pre/Post rotator/mirror
This IP core embeds Chips&Media's proprietary 16-bit DSP processor dedicated to processing bitstream and controlling their video HW
General-purpose registers and interrupts for communication between a host and processor and the video IP
Configurable frame buffer formats (linear or tiled) for longer burst-length
2D cache for motion estimation and compensation to reduce external memory accesses
Secondary AXI port for on-chip memory to enhance performance

Block Diagram

Applications

Various consumer electronics:
Smartphones
Media tablets
Multimedia players
Desktop & laptop
Digital set-top boxes
Video game consoles
Surveillance camera
Driving recorders
Automotive infotainment
AR/VR and more!

Deliverables

RTL source code
Datasheet
Verification Guide
API Reference Manual
Programmer's Guide
C-model User's Guide

Technical Specifications

Availability

Now

TSMC

Pre-Silicon: 7nm

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