ETHERNET 1G PCS IP

Overview

Key Features

• Supports PCS functionality compliant with IEEE Standard 802.3.2018 Clause 36
• Supports TBI Interface
• Supports 10/100/1000M and SGMII
• Supports Frame encapsulation at Transmit PCS and de capsulation at Receive PCS
• Supports synchronization on Receive PCS (Reporting of various error statistics)
• Supports generation of carrier sense and collision detection to GMII Interface
• Supports IEEE Standard 802.3.2018 Clause 37 Auto negotiation
• Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
• Supports Configurable Management Interface (MDIO(Clause 22) / SOC Bus)
• Supports Loopback Functionality
• Supports Transmit and Receive rate adaptation in SGMII Interface
• Optional support for Auto negotiation with Next page
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The Ethernet interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications