ETHERNET 10G TSN MAC IP
Overview
Ethernet 10G TSN MAC core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet TSN IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 10G TSN MAC IIP is proven in FPGA environment. The host interface of the Ethernet can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Key Features
- Compliant with IEEE Standard 802.3-2018 Specification - Clause 46
- Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
- Supports timing synchronization as per IEEE Standard 802.1 AS
- Supports Traffic Scheduling - IEEE Standard 802.1Qbv(Enhancement for Scheduled Traffic) and IEEE Standard 802.1Qav (Credit Based Shaping)
- Supports class based flow control and class based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
- Supports Full duplex mode of operation
- Ultra low latency and compact implementation
- Supports MDIO (Clause 22 and Clause 45) Interface
- Supports Programmable Inter Packed Gap(IPG) and Preamble length
- Supports XGMII (32 bit) interface
- FCS generation supported
- Supports VLAN and jumbo frames as an option
- Independent TX and RX Maximum Transmission Unit (MTU)
- TSN features can be enabled/disabled independently
- Cut-through support
- Configurable Transmit and Receive FIFOs
- Comprehensive statistics gathering
- Supports 32bit AXI4 Stream for Packet data
- In house UNH compliance tested
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
- The Ethernet interface is available in Source and netlist products
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User s Guide and Release notes
Technical Specifications
Maturity
Getting used at customer site