eFPGA IP and FPGA Software Built on GLOBALFOUNDRIES 22FDX

Overview

Key Features

• High-performance architecture for low power applications
• Super Logic Cell (SLC) clusters 4 logic cells together with hierarchical routing networks for optimum performance and power consumption
• Each logic cell can be used as two separate 4-input LUTs or one 5-input LUT.
• Direct input selection to the register allows combinatorial and sequential logic to be used separately.
• Multiple outputs per logic cell are strategically selected to either feedback within the same SLC or to travel out to another SLC. A shared register clock, set, and reset signals for all four logic cells helps reduce routing congestion.
• Array sizes ranging from 8×8 SLC up to 64×64 SLCs

Benefits

• Expand addressable market of your SoC through on-chip reprogrammability
• Market test new features and functions before committing to hard gates or custom silicon
• Protect your ASIC by using the eFPGA as a reprogrammable isolation area for security or authentication IP
• Extends product longevity and hardware-based Continuous Integration (CI)

Block Diagram

Technical Specifications