QuickLogic's latest eFPGA architecture designed from the ground up for MCU/SoC/custom ASIC applications - optimized for edge and endpoint AI processing, military, aerospace and automotive
QuickLogic's newest eFPGA architecture, completely designed for embedding into low power SoCs, the eFPGA architecture includes hierarchical logic and routing plus acceleration building blocks such as embedded memory and multiplier-accumulates (MACs).
eFPGA IP and FPGA Software Built on Samsung Foundry 28nm FDSOI
Overview
Key Features
- High-performance architecture for low power applications
- Super Logic Cell (SLC) clusters 4 logic cells together with hierarchical routing networks for optimum performance and power consumption
- Each logic cell can be used as two separate 4-input LUTs or one 5-input LUT.
- Direct input selection to the register allows combinatorial and sequential logic to be used separately.
- Multiple outputs per logic cell are strategically selected to either feedback within the same SLC or to travel out to another SLC. A shared register clock, set, and reset signals for all four logic cells helps reduce routing congestion.
- Array sizes ranging from 8×8 SLC up to 64×64 SLCs
Benefits
- Homogenous Fabric architecture
- Super Logic Cell (SLC) consisting of
- 8 LUT4
- 8 registers
- Hierarchical routing networks for optimum performance and power consumption
- eFPGA arrays range from 8x8 to 64x64 SLCs
- ~500 LUT4s to 32K LUT4s
- Built in Block RAM
- Fracturable Multiplier-Accumulates (MACs)
Technical Specifications
Foundry, Node
Samsung Foundry 28nm FDSOI
Samsung
Pre-Silicon:
28nm
FDS
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