Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane

Overview

* The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams. A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link. The polarity of differential signals for each data lane can be controlled. The transmit clock frequency of 160MHz, 24bits RGB data, and 4bits LCD timing & control data (HSYNC, VSYNC, DE,Control1) are transmitted at the rate of 1.12Gbps per LVDS data lane. The CL12491M8TIP160 transmitter is an ideal means to solve EMI and cable size issues associated with high-speed CMOS interface.
The CL12491M8TIP160 has integrated PLL with spread spectrum clock option. The targeted SSC modulating frequency is designed to be in the range of 10KHz ~ 30KHz, with modulation depth up to 3.1%, centered spread.
* This IP can also be optimized for single-link use.
* Porting is also possible for processes other than the target process.

Key Features

LVDS Operational modes supported:

to support 1080p@60fps with single link (4 data lanes + 1 clock lane)
to support 2560x1440 @60fps with dual link (8 data lanes + 1 or 2 clock lane)

Data Rate: Up to 1.12Gbps
Clock polarity programmable
Data polarity for each data lane is programmable
Integrated PLL with spread Spectrum option
4 programable level of output differential voltage
RX detection circuit to detect connectivity to device
Clock-in-fail detection to detect malfunction of clock source
BIST function for loopback test

Benefits

By implimenting the CL12491M8TIP160 in an SOC, it easily realizes the function of converting parallel RGB data and 4-bit CMOS parallel data to LVDS data stream. It can support displays with resolutions of FHD (single link) and WQHD (dual link). The built-in PLL with spread spectrum clock option makes it easy to reduce EMI in the set.
Process porting is available according to customer requests.
This IP can be implemented in a lane units and can be tailored to meet customer specifications.

Applications

Display Application

Automotive
Navigation system
DSC(Digital Still Camera)

Deliverables

Verilog Model (verilog / vcs)
.db file / .lib(Option) file
symbol / LVS netlist / Hspice netlist(Option)
LEF, layer map file, layout technology file
Layout Verification Report (DRC & LVS), Command file
Datasheet
Packaging and Layout Guideline / PCB Guideline
Static Delay Analysis (STA) Guideline
Testing Guideline (Option)

Technical Specifications

Foundry, Node

TSMC 16nFFC

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 16nm

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