The DDR5 LRDIMM Verification IP provides an effective & efficient way to verify the components interfacing with DDR5 LRDIMM interface of an ASIC/FPGA or SoC. The DDR5 LRDIMM VIP is fully compliant with Standard DDR5 specification, DDR5 Memory Buffer specification & DDR5 RCD specification from JEDEC. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
DDR5 LRRDIMM Verification IP
Overview
Key Features
- Compliant to JEDEC DDR5 SDRAM Specification, Data Buffer & RCD Specification.
- Supports connection to any DDR5 Memory Controller IP communicating with a JEDEC compliant DDR5 Memory Model.
- Supports configurable SDRAM addressing of different sizes (x4, x8 and x16).
- Available in all memory sizes up to 64 Gb.
- Supports for all speed-grades/speed-bins.
- Supports configurable timing parameters and rank associations.
- Supports 3DS with command to command timings checks in SLR & DLR.
- Supports all Command Address Rates (SDR1, SDR2 & DDR).
- Supports BCOM Training Mode, Strobe & Data Trainings, DCATM, DCSTM, QCATM, QCSTM & Enhanced DCATM. AXI In AXI Seq AXI Master APB/AHB seq APB/AHB Master APB/AHB In DFI In Memory Controller BFM/DUT DFI-PHY BFM/DUT DDR In DFI Monitor Functional Coverage Asser ons Transac on Logger APB Master APB Seq DFI Monitor Functional Coverage Asser ons Transac on Logger Memory BFM/DUT I2C SPD TS PMIC DIMMs
- Supports CA parity for command/address bus.
- Supports Control Word decoding, write & read.
- Supports Data Masking (DM).
- Supports Cyclic Redundancy Check (CRC).
- Supports Programmable burst lengths.
- Supports capturing all the valid DDR5 commands including Activate, Read Write, Precharge.
- Supports Power-up Reset and initialization sequences.
- Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation (with and without clock stop).
- Reports various timing errors, which can be used to check timing violations.
- Provides full control to the user to enable/disable various types of messages.
- Support for Multiple Ranks architecture.
- Supports advanced System Verilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
- Graphical analyzer to show transactions for easy debugging.
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- 24X5 customer support & response under 90 Min.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy.
Block Diagram
Deliverables
- DDR5-SDRAM Model, RCD Model & Data Buffer Model
- DDR5 Monitor & Scoreboard
- DDR5 Memory Controller BFM/Agent
- DDR5 PHY BFM model
- DDR5 Phy Monitor and Scoreboard
- Test-Bench Configurations
- Test Suite (Available in Source code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes