The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decryption core.
Designed for fast integration, low gate count, and maximum performance, the EIP-13 provides a reliable and cost-effective ChaCha20 IP solution that is easy to integrate into SoC designs.
ChaCha20 Crypto Accelerator
Overview
Key Features
- Wide bus interface
- 128-bits and 256-bits key sizes
- 32-bits counter and 64-bits counter modes
- CTR feedback mode
- Fully synchronous design
- High Speed and high frequency configurations
Benefits
- High-speed ChaCha20 solution.
- Silicon-proven implementation.
- Fast and easy to integrate into SoCs.
- Flexible layered design.
- Complete range of configurations.
- World-class technical support
Applications
- TLS3.1
Deliverables
- Documentation
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Configurations:
- Configurations:
- EIP-13a
- Medium-speed Encrypt/Decrypt
- 24.38 bits/clk
- 24.7k gates
- up to 525 MHz
- EIP-13b
- Low-speed, High-frequency
- 12.48 bits/clk
- 28.5k gates
- up to 825 MHz
- EIP-13c
- High-speed, Low-frequency
- 46.5 bits/clk
- 31.8k gates
- up to 300 MHz
- EIP-13d
- Low-speed, Low gate count
- 12.48 bits/clk
- 21.9k gates
- up to 525 MHz
Technical Specifications
Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven:
7nm
,
16nm
,
28nm
,
40nm
G