AES-ECB-CBC-CFB-OFB-CTR-GCM-XTS-CCM Crypto Accelerator

Overview

The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the basic feedback modes such as CBC, CFB, OFB, and CTR, the EIP-39 also provides CCM and CMAC and optionally GCM, XTS, f8 and f9.

Designed for fast integration, low gate count, and maximum performance, the AES Engines provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs. The EIP-39 core is also available in configurations with protection for Side Channel Attacks, including Fault Injection. These provide additional protection against attacks in environments in which the SoC can be attacked, while its active keys may not be revealed.

Key Features

  • Register interface.
  • Key sizes: 128, 192 and 256 bits.
  • Key scheduling hardware.
  • Feedback modes: ECB, CBC, CFB, OFB, CTR.
  • Protocol modes: CCM, CMAC and XCBC-MAC
  • Optionally available: GCM, XTS, f8 and f9.
  • Low Speed, Medium Speed, High Speed versions.
  • Fully synchronous design

Benefits

  • High-speed AES-CCM solution
  • Silicon-proven AES implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Applications

  • IoT security

Deliverables

  • Documentation
    • Hardware Reference and Programmer Manual
    • Integration Manual
    • Verification Specification
  • Synthesizable Verilog RTL source code
  • Self-checking RTL test bench, including test vectors and expected result vectors
  • Simulation scripts
  • Configurations:
    • EIP-39b
      • High-speed CCM
      • 35k gates
      • 5.81 bits/clk (CCM), 12.8 bits/clk (Other)
      • up to 550 MHz
    • EIP-39d
      • Medium-speed CCM
      • 29k gates
      • 1.93 bits/clk (CCM), 4.00 bits/clk (Other)
      • up to 700 MHz
    • EIP-39f
      • Low-speed CCM
      • 27k gates
      • 1.20 bits/clk (CCM), 2.46 bits/clk (Other)
      • up to 700 MHz
    • EIP-39b-g-(-buf or -nobuf)
      • High-speed CCM+GCM
      • -buf: 46k gates, -nobuf: 45k gates
      • 11.63 bits/clk (CCM), 5.81 bits/clk (GCM), 12.8 bits/clk (Other)
      • up to 550 MHz
    • EIP-39d-g-(-buf or -nobuf)
      • Medium-speed CCM+GCM
      • -buf: 36k gates, -nobuf: 34k gates
      • 3.87 bits/clk (CCM), 1.93 bits/clk (GCM), 4.00 bits/clk (Other)
      • up to 700 MHz
    • EIP-39g
      • Low-speed CCM+GCM
      • 33k gates
      • 2.41 bits/clk (CCM), 1.20 bits/clk (GCM), 2.46 bits/clk (Other)
      • up to 700 MHz
    • EIP-39f-f8-x
      • Low-speed CCM+XTS+f8
      • 28k gates
      • 1.20 bits/clk (CCM), 2.46 bits/clk (Other)
      • up to 700 MHz

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP