ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security IP

Overview

PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers to their use in consumer electronics. PCI Express links carry high value information between the host and the peripheral and from endpoint to endpoint.
The Synopsys Integrity and Data Encryption (IDE) Security IP Module for PCIe
5.0 provides confidentiality, integrity, and replay protection for Transaction Layer Packets (TLP) over PCI Express interfaces as defined in the PCI-SIG IDE specification. The security module integrates seamlessly with the Synopsys PCIe 5.0 controllers to accelerate SoC integration.

Benefits

Compliant with PCI Express IDE specification
High-performance AES-GCM based packet encryption, decryption, authentication
Seamless integration with Synopsys controllers via TLP packet-based interface
Support for PCIe 5.0, 4.0 and 3.0 data rates
Customer configurable
Aligns with PCIe controller’s configuration options
Scalable data bus width: 128, 256, 512
Lanes: x1, x2, x4, x8, x16
optimized for area, performance & latency’ bullet saying
Support for TDISP
Optimized for area, performance & latency
Multi-stream support
PCRC calculation & validation
Efficient key control & refresh

Applications

High performance computing
Cloud computing: data centers, enterprise, storage area networks, SSDs, networking switches, routers
Artificial intelligence / deep learning
Graphics
Mobile multimedia
Gaming
Industrial

Deliverables

Synthesizable RTL developed in compliance with the IEEE1364 Verilog-2005 standard
Verilog integration testbench
Sample synthesis script and constraints
Sample simulation script
Databook
Hardware user guide
Hardware installation guide

Technical Specifications

Maturity

Available on request

Availability

Available

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