800MHz General Purpose PLL

Overview

Key Features

• Wide range M, P integer dividers.
• 50MHz – 800MHz output frequency range.
• Compare frequency range 8MHz – 32MHz.
• 15pS RMS cycle to cycle jitter at 800MHz.
• Lock-detect function.
• Bypass function.
• Well-defined, fast startup behavior.
• -40°C to 140°C temperature operation.
• Available divider selection program.
• Small area: 0.03mm2 in 0.152µ CMOS.
• 3mW typical power dissipation.
• 1.8V digital and analog supplies.
• 0.152µ CMOS process compatibility.
• Silicon proven many times.
• Mature architecture.

Block Diagram

Applications

• Crystal frequency to device internal clock multiplication.
• Communication cores.
• Bus Interface cores.

Deliverables

• Verilog model.
• Metal outline.
• Spice netlist for LVS.
• Design review spice files.
• GDS.
• Timing files.
• Integration notes.
• Production test notes.

Technical Specifications