The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from — or even the presence of — a system processor.
The core acts either as a server or a client and without any assistance from the host autonomously system, opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces.
The highly configurable core can adapt to different applications and diverse system requirements. The maximum number of simultaneous TCP sessions is configurable at synthesis time; it can be as high as 32,768 for devices like data servers, or as small as 1 for edge devices requiring minimum silicon area and power. Further user options include implementing a DHCP client that allows the core to automatically be assigned an IP address, enabling or disabling support the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack with multicast support (IGMPv3). Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets but it will have higher latency and require more memory resources.
The TCPIP-1G/10G core is rigorously verified and available in RTL source or as a targeted FPGA netlist. Its deliverables include a testbench, synthesis and simulation scripts, and comprehensive user documentation.
1G/10G TCP/IP Hardware Stack
Overview
Key Features
- Complete TCP/IP Hardware Stack
- 10/100/1000, 2.5G, and 10G Ethernet Transmit and Receive
- TCP server or client with up to 32k simultaneous TCP sessions
- Autonomous and highly efficient TCP connection establishment, maintenance and teardown, retransmission, flow and congestion control
- Optional out-of-order TCP packet reassembly
- Checksums generation and validation
- IPv4 support
- Jumbo and Super Jumbo Frames
- ARP with Cache, ICMP (Ping Reply), VLAN (IEEE 802.1Q),
- UDP, IGMP, and DHCP (optional)
- Trouble-Free Operation
- Highly flexible thanks to runtime programmable options including:
- Local MAC address, IP address, Gateway IP address, and IP subnet mask
- IP Address, & Port Filters
- Retransmission timeouts, limits, and enable/disable of fast retransmission
- Cut-through or store & forward processing
- Flow control and congestion control
- Window sizes, MSS
- Non-TCP/UDP IP traffic is optionally forwarded to the system via a dedicated port
- Easy SoC Integration
- Standardized AMBA interfaces:
- 64-bit AXI4-Stream for packet data
- 32-bit AXI4-Lite for CSR (APB3 optional)
- 256-bit AXI4 for external memory
- Separate clock domains for packet processing and CSR interfaces
- Independent from external memory type and controller, and from the ethernet MAC or PHY.
- Optionally pre-integrated with Intel, Xilinx, or other third-party eMAC cores
- Versions & Configuration Options
- Maximum number of simultaneous TCP sessions (up to 32K)
- Cut-through for minimum latency, and memory size but without out-of-order TCP packets support
- Deliverables
- Synthesizable RTL or FPGA netlist
- UVM Testbench & sample test cases
- Simulation & synthesis scripts
- Documentation
Block Diagram
Deliverables
- The TCPIP-1G/10G core is available in synthesizable Verilog RTL and FPGA netlist forms. Its deliverable package includes everything required for successful implementation:
- Comprehensive user documentation,
- A highly sophisticated UVM testbench,
- Sample synthesis and simulation scripts, and
- A software driver with an easy-to-use API
- Sample designs integrating the TCPIP-1G/10G with third-party or CAST's Ethernet MAC and/or memory controller IP cores are available upon request. Such integrated designs are readily available for devices from all the major FPGA vendors. Please contact CAST to learn more details.