10G Ultra-low latency MAC + PCS IP core for FPGAs

Overview

Key Features

• Management of layers 1 and 2 (OSI Model), compliant with
• Layer 1: IEEE802.3
• Layer 2: IEEE802.3, ARP (Address Resolution Protocol)
• Multiple Interface
• Up to 8 logical interfaces per instance
• Avalon/AXI-4 Streaming
• 64-bit wide interface running at 250 MHz for MAC client port
• IP configuration/management
• 32-bit Avalon-MM/AXI- 4 lite slave control interface for MAC configuration
• Status and statistics available for monitoring at MAC session level
• PHY Interface
• PMA Parallel Data between PCS and vendor PMA (PMA Direct Mode for Altera
• MII 64-bit Streaming Interface between PCS and MAC

Benefits

• Best-in-class latency from the wire to the user’s own logic.
• 10G Ethernet connectivity. Maximum bandwidth delivered.
• Full RTL Enyx proprietary ultra-low latency hardware MAC and PCS implementations.
• Clock configurable at up to 250 MHz, for improved latency results.
• Easy to use standardized Avalon and AXI-4 interfaces.
• Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique MAC address.

Block Diagram

Deliverables

• nxMAC + nxPCS IP Core
• Libraries for functional simulation
• Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation
• nxMAC + nxPCS Testbench
• Simulation libraries
• Client-Server Reference Designs
• Simulation environment and scripts
• Quartus II and Vivado Synthesis/implementation project for supported partner’s boards
• Complete Documentation
• User’s manual
• Getting started guide
• Technical Support and Maintenance Updates
• 1 year of technical support
• 1 year of IP updates

Technical Specifications