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Die-to-Die PHY
- 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD)
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Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
- Data rates of up to 4Gbps per pin
- Self-contained hard macro
- Self-calibrating RX sampling phase and threshold selection
- Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
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Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
- Offers leading performance, power, and area / beachfront per terabit
- Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
- Targeting the OIF XSR standards: CEI-112G and CEI-56G
- Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
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Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
- Offers leading performance, power, and area / beachfront per terabit
- Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
- Targeting the OIF XSR standards: CEI-112G and CEI-56G
- Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
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Die-to-Die (D2D) Interconnect
- Adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies
- Architected to significantly reduce wiring overhead across multiple dies
- Supports transfer rates of up to 6.4GT/s
- Supports major 2.5D and 3D inter-die packaging technologies
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TSMC CLN6FF/7FF Die-to-Die Interface PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- Lane repair
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TSMC CLN5FF Glink 2.0 Die-to-Die PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- VALID and READY handshake mechanism
- Flow control between TX and RX