USB 2.x Host IP

Overview

Key Features

• Compliant with USB 2.0 specification.
• Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
• ->Asynchronous Park-mode
• ->Three caching models: no caching, micro-frame caching and frame caching
• ->NAK counter to limit unnecessary memory accesses
• ->Descriptor and data pre-fetch, pre-compute and cache
• Supports UTMI and ULPI transceivers.
• Operates at High-speed (480 Mbps), Full-speed (12 Mbps) and Low-speed (1.5 Mbps).
• Attach/detach, reset signaling and suspend/resume.
• Enumeration of low-speed, full-speed, and high-speed devices.
• All USB 1.1 transfer types are supported.
• Supports Interrupt/Bulk/Isochronous/Control Transfers.
• CRC16 checking and generation for HS/FS/LS data packets.
• CRC5 generation and checking for Tokens.
• Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.
• Supports preamble for LS transfers while operating in Embedded Host Mode.
• Supports Protocol Layer Error Handling.
• Provides prioritized scheduling for periodic endpoints.
• Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• Supports USB Suspend state and supports remote wakeup devices.
• Supports all HS/FS USB Link Power Management States – L1, L2.
• Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
• Support for clock gating and multi-power-well support
• DMA interface with configurable burst length supporting high-speed data transfers between USB Host and AXI/AHB/APB/OCP host.
• Direct addressing of all IP Core registers from AXI/AHB/APB or OCP bus.
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The USB2.x Host interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications