UART with FIFOs

Key Features

• Capable of running all existing 16450 and 16550a software
• Fully Synchronous design. All inputs and outputs are based on rising edge of clock
• In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock
• Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
• Fully programmable serial interface characteristics:
• 5, 6, 7, or 8 bit characters
• Even, odd, or no-parity bit generation and detection
• 1, 1½, or 2 stop bit generation
• Baud generation
• False start bit detection
• Complete status register
• Internal diagnostic capabilities: loopback controls for communications link fault isolation
• Full prioritized interrupt system controls

Benefits

• Developed for easy reuse in ASIC and FPGA applications.
• Available options:
• - AMBA bus interface
• - OCP bus interface

Deliverables

• VHDL or Verilog RTL source code, or targeted FPGA netlist
• Testbenches (self checking)
• Example testbench wrapper for post-route simulation
• Simulation script
• Synthesis script
• Documentation

Technical Specifications