IP Catalog > Interface IP > Interconnect IP > Serdes IP > TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes

TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes

Overview

The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and analogous standards. The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 10/16/20/32/40/50/64-bit width data bus. The transmitter, similarly, serializes selectable 10/16/20/32/40/50/64-bit width data bus and drives the serialized data off-chip with built-in adjustable de-emphasis (FFE). EMS-PHY SerDes includes the physical media attachment layer (PMA) which is implemented as a hard macro and the physical coding sub-layer (PCS) which may be licensed separately through GUC or its 3rd party partners.

Key Features

  • PMAA (PMA Analog)
  • RX Adaptive Decision Feedback Equalizer (DFE)
  • Programmable Continuous Time Linear Equalizer (CTLE)
  • RX Variable Gain Control
  • RX Built-in fault detector (Loss of Lock/Loss of Signal)
  • Adjustable TX de-emphasis (FFE)
  • TX output amplitude control
  • Supports RX Eye Monitor
  • Supports JTAG 1149.6 boundary scan interface
  • PMAD (PMA Digital) & Testability
  • Built-in BIST functions (PRBS7, PRBS9, PRBS11, PRBS15, PRBS23, PRBS31 and User-Defined generators & checkers, etc.)
  • Polarity inversion and bit reversal control
  • Multiple Loopback modes
  • Status registers
  • Selectable TX/RX Data bit width control (10/16/20/32/40/50/64)
  • LOL (Loss of Lock) detection
  • LOS (Loss of Signal) detection

Technical Specifications

Foundry, Node
TSMC 12nm CLN12FFC
Maturity
Avaiable on request
TSMC
Pre-Silicon: 12nm
Request Info

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