The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus.
A SPI Slave to AHB Lite Interface block provides read/write access by an external SPI device to the various memories and registers that are present in the chip's internal AHB Lite subsystem. The Bridge converts SPI transactions into AHB Read or Write instructions, allowing the external SPI device to have full access to all memory mapped devices present in the AHB Lite subsystem.
The SPI protocol layer is responsible for several things including:
- Interpreting commands from the low-level SPI interface (R/W, address, mode, protection, burst length).
- Generating an AHB Read or Write transaction based on the command
received from the SPI interface.
- Presenting (parallel) address and write data from the low-level SPI interface to the system.
- Presenting (parallel) read data from the system to the low-level SPI interface.
SPI Slave to AHB Lite Master
Overview
Key Features
- AMBA® AHB Monitor
- Allows external devices to access the internal AHB Bus
- AHB Master Read/Write capability
- Useful for updating device software from and external device
- Useful for reading internal memory mapped registers and memory
Block Diagram
Deliverables
- Verilog Source
- Complete Test Environment
- AHB Bus Functional Model
- C-Sample Code
Technical Specifications
Maturity
Silicon Proven
Related IPs
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa
- A bridge to convert the slave SPI interface to the master UART interface and vice versa
- SPI Slave To AHB Bridge IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (APB Bus)