SM4 Crypto Accelerator
Overview
The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for fast integration, low gate count, and maximum performance, the SM4 Engine provides a reliable and cost-effective SM4 IP solution that is easy to integrate into SoC designs.
Key Features
- Register interface.
- Key size: 128 bits.
- Key scheduling hardware.
- Supported modes: ECB.
- Low Speed, Medium Speed, High Speed versions.
- Fully synchronous design.
Benefits
- High-speed SM4 solution.
- Silicon-proven implementation.
- Fast and easy to integrate into SoCs.
- Flexible layered design.
- Complete range of configurations.
- World-class technical support
Applications
- Chinese algorithm
Deliverables
- Documentation
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Configurations:
- EIP-12a
- High-speed Encrypt/Decrypt
- 16.00 bits/clk
- up to 400 MHz
- 38.6k gates
- EIP-12b
- Medium-speed Encrypt/Decrypt
- 8.00 bits/clk
- up to 600 MHz
- 24.2k gates
- EIP-12c
- Low-speed Encrypt/Decrypt
- 4.00 bits/clk
- up to 860 MHz
- 18.3k gates
- EIP-12d
- Low gate count
- 0.795 bits/clk
- up to 1 GHz
- 15.8k gates
Technical Specifications
Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven:
7nm
,
16nm
,
28nm
,
40nm
G