SM3 Crypto Accelerator

Overview

The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic. Designed for fast integration, low gate count, and maximum performance, the SM3 Engine provides a reliable and cost-effective SM3 IP solution that is easy to integrate into SoC designs.

Key Features

  • Register interface.
  • Widebus interface with native algorithm bus widths.
  • Message padding functionality.
  • Hash context switching
  • Hash continuation support.
  • High-speed, medium-speed and low gate count SM3 solutions.
  • Fully synchronous design

Benefits

  • High-speed SM3 solution.
  • Silicon-proven implementation.
  • Fast and easy to integrate into SoCs.
  • Flexible layered design.
  • Complete range of configurations.
  • World-class technical support

Applications

  • Chinese algorithm
  • OSCCA
  • Hash
  • Authentication
  • SHA

Deliverables

  • Documentation
    • Hardware Reference and Programmer Manual
    • Integration Manual
    • Verification Specification
  • Synthesizable Verilog RTL source code
  • Self-checking RTL test bench, including test vectors and expected result vectors
  • Simulation scripts
  • Configurations:
    • EIP-52a
      • High-speed
      • 32.00 bits/clk
      • up to 300 MHz
      • 35.4k gates
    • EIP-52b
      • Medium-speed
      • 16.00 bits/clk
      • up to 500 MHz
      • 26.3k gates
    • EIP-52d
      • Low gate count
      • 7.76 bits/clk
      • up to 750 MHz
      • 18k gates

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
×
Semiconductor IP