RTP/UDP/IP Hardware Stack for H.264 NAL Video

Overview

Key Features

• RTP/UDP/IP Protocol Hardware Stack, targets H.264 NAL Streams. See DB RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams 
• Internet Protocol (IP) Packet Processor:  
  • IPv4 and IPv6 (optional) & ICMP (Internet Control Message Protocol) Protocol 
  • IP header checksum generator (transmitter) & check (receiver), user selectable Maximum Transmission Unit (MTU), Unicast, Broadcast &  Multicast Packet support 
  • Compliance with IETF IPv4/IPv6 RFCs 
• User Datagram Protocol (UDP) Packet Processor: 
  • UDP header checksum generator (transmitter) & check (receiver) – programmable on/off 
  • Compliance with IETF UDP RFCs 
• Real Time Transport Protocol (RTP) Packet Processor 
  • Multiple TX/RX NAL streams supported 
  • For RX, optional Packet reordering to absorb network jitter 
  • Compliance with IETF RTP RFCs 
• Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache 
• High Speed Data Interface to user Host Application (typical clock rates): 
  • 10/100/1000 MbE: 32-bit @ 2.5/25/125 MHz, AXI4-Stream or Avalon-ST 
  • Contact Digital Blocks regarding 10 GbE higher network requirements 
• Host set-up & control via Control & Status Registers and Interrupt Controller 
  • 32-bit @ user clock rate AXI4-Lite or Avalon-MM  
  • Optional hardwired no-register setup 
• Pipeline, High Clock Rate, Low Latency architecture & design 
• Fully synchronous, synthesizable RTL Verilog SoC IP core 
   

Block Diagram

Deliverables

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

Technical Specifications