PCIe3.0 Controller

Overview

Key Features

• Fully compliant with PCI Express Base Specification Revision 3.0.
• Fully compliant with PIPE Specifications Revision 4.4.1
• Support Root Complex and Endpoint Mode.
• Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps)
• Support x1 x2 x4 x8 x16(according to request)
• Internal Address Translation
• AXI4 Address-64bits Data-64bits
• PIPE-32bits Dynamic Frequency
• Max Payload Size 512 bytes
• Embedded DMA
• Automatic Lane Reversal
• Advanced Error Reporting (AER)
• ASPM L0s, L1
• L1 Substates (L1SS) with CLKREQ
• MSI/INTx
• 1 Virtual Channel (VC)
• ECRC generation and check
• ID-Based Ordering (IDO)

Benefits

• Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
• Supports 2.5/5.0Gb/s serial data transmission rate
• Utilizes a 16-bit or 32-bit interface to transmit and receive PCI Express data
• Allows integration of high speed components into a single functional block.
• Data and clock recovery from serial stream on the PCI Express bus
• Holding registers to stage transmit and receive data
• Supports direct disparity control for use in transmitting compliance pattern
• 8b/10b encode/decode and error indication
• Receiver detection
• Beacon transmission and reception
• Selectable Tx Margining, FFE and signal swing values
• Built in self-test and loopback test
• Selectable Tx Margining and FFE taps
• Selectable Rx CTLE peaking range and DFE taps
• Auto calibrated and tunable on die termination (ODT)
• Integrated IO with ESD protection aimed at HBM 2KV, MM 100V and CDM 250V
• Well-tuned T-coil to promote ultra-high bandwidth

Deliverables

• Databook
• Encrypted simulation model
• Netlist
• SDC Files

Technical Specifications