Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical Layer protocol aware Retimer is to execute the Phase 2/3 of the equalization procedure in each direction. Compliant with pipe specification.
PCIe Gen6.0 Retimer
Overview
Key Features
- Compliant with PCIE Gen6/5/4 Specs.
- Compliant with Pipe 5.X Spec
- Forward mode supported.
- Execution mode for Equalization, Loopback and Compliance are supported.
- X1, X2, X4, X8, X16 lanes supported.
- Lane bifurcation supported.
- Lane polarity thru register control.
- PIPE 64bit Serdes interfaces.
- APB interface for register configurations.
- Lane deskew supported.
- Support for L1 states.
- SKP OS add/removal.
- SRIS mode supported.
- No equalization support thru configuration.
- De-emphasis negotiation support at 5GT/s.
- EI inferences in all modes.
- Automatic adjustment of data rates in conjunction with upstream and downstream devices.
- Automatic adjustment of link width in conjunction with upstream and downstream devices.
Deliverables
- Verilog soft IP
- Sample testbench
Technical Specifications
Availability
Immediate