PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture

Overview

Key Features

• Supports all required features of the PCI Express 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
• Full Transaction Layer, Data Link Layer and Physical Layer
• Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
• Available in 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
• 125 MHz, 250 MHz, 500 MHz, 1 GHz and 2 GHz operation
• Supports PIPE 6.x interface including variable clock and variable data widths up to 64-bit
• Application interfaces include the Synopsys native interface or the optional single- or dual-port 512-bit/1024-bit AXI Bridge supporting Arm AMBA 5/4/3 AXI
• Optional embedded HyperDMA controller with up to 64 read and 64 write channels plus descriptor pre-fetch for high throughput with minimal SoC resource overhead
• Configurable and efficient retry buffer design for low latency and area
• Supports automatic lane reversal and polarity inversion
• Supports the full range of PCIe-defined maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB)
• Performs PCI Express flow-control credit management, configurable for infinite credits for any traffic type
• Supports legacy INTx, MSI, and MSI-X interrupt semantics
• Configurable filtering rules for posted, non-posted and completion traffic
• Configurable BAR (up to 6) filtering, IO filtering, configuration filtering and completion lookup/timeout
• Support for multiple application clients
• In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
• Expansion ROM, VPD, and Device Serial Number support
• Broad support for optional ECNs

Benefits

• Synopsys Controller IP for PCI Express provides a complete set of features which enable the user to define an optimized PCI Express interface in products across the full spectrum of applications.
• Mobile and other low-power designs benefit from full support of ASPM Power Management as well as key optional PCIe features such as:
• L1 sub-states for PHY power savings
• Beacon and wake-up mechanisms
• Latency Tolerance Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF) ECN support
• Power gating (retention and power island) support via UPF flows
• With PCI Express storage dominating today’s client and enterprise markets, the Synopsys Controller IP for PCI Express supports PCIe features critical to effective implementations of these and other products requiring extreme robustness:
• Ultra-low transmit and receive latency and high accessible bandwidth
• RAS data protection providing ECC and/or Parity protection for internal buses and memories
• Advanced debug capabilities for error injection and statistical monitoring
• Separate Reference Clock with Independent Spread (SRIS) ECN support
• Configurable ECRC generation and checking
• Building atop those features, the controller IP offers additional performance and virtualization features for a variety of enterprise class implementations:
• Supports up to 8 virtual channels and up to 8 traffic classes
• Directly supports up to 32 physical functions and up to 256 virtual functions using SR-IOV and ARI – Optional extension up to 64K Virtual Functions
• Supports up to 15,360 outstanding PCI Express requests using 14-bit tags
• TLP Processing Hints (TPH), ID-based Ordering (IDO), Atomic Operations, and Resizable BAR ECNs
• To protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express (PCIe) 6.0 interface, Synopsys will offer standards-compliant Integrity and Data Encryption (IDE) Security IP Modules.
• Designed and validated with Synopsys’ Controller IP for PCIe 6.0 to accelerate SoC integration
• Provide data confidentiality, integrity, and replay protection
• Protect sensitive data with efficient encryption, decryption, and authentication based on AES-GCM algorithms while meeting PCIe
• 6.0 designs’ performance and latency requirements
• TDISP support for PCIe for SR-IOV and hardware security via IDE

Applications

• High-performance computing (HPC), storage area networks, networking switches, routers
• Artificial Intelligence (AI)

Deliverables

• The coreConsultant utility to guide designers through the installation configuration, verification, and implementation of the IP; Verilog RTL code; Example PHY interfaces; ASIC and FPGA synthesis scripts; Verification environment; Synopsys Verification IP for PCI Express; Documentation: release notes, installation/integration guide, application notes, user manual

Technical Specifications