MIPI RFFE Slave IP
Overview
MIPI RFFE Slave interface provides full support for the two-wire MIPI RFFE synchronous serial interface, compatible with RFFE specification. Through its RFFE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI RFFE Slave IIP is proven in FPGA environment.The host interface of the MIPI RFFE can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Key Features
- Compliant with version 3.0 MIPI RFFE Specifications.
- Full MIPI RFFE Slave functionality.
- Supports following frames
- -> Command Frame
- -> Data/Address Frame
- -> No Response Frame
- Supports extended register read/writes
- Supports interrupt summary and identification command sequence
- Support Trigger and Extended trigger modes
- Support Masked write command sequence
- Supports Timed Trigger
- Supports Mappable Triggers
- Support Synchronous read
- Support Normal and Secondary operation mode
- Support USID Programming Procedure 1,2 and 3
- Support Group slave ID
- Supports device enumeration
- Supports Half-Speed Data Response (HSDR) Accesses
- Supports Full Command Sequence at Half-Speed SCLK
- Supports Delayed Read-back
- Supports Reserved Register Allocations in Basic Address Space (0x1C â?? 0x1F)
- Supports Reserved Register Allocations in Extended Address Space (0x20 â?? 0x3F)
- Supports Write Slave State via PWR_MODE bits
- Supports Read Slave State via PWR_MODE bits
- Supports Read PRODUCT_ID, MANUFACTURER_ID and USID from reserved registers.
- Support Interrupt capable slave
- Supports Extended Frequency Range up to 52 MHz
- Supports Error detection
- -> Undefined command frame
- -> Command frame with parity error
- -> Command frame length error
- -> Address frame with parity error
- -> Data frame with parity error
- -> Read of unused register
- -> Write of an unused register
- -> Read using the broadcast ID or a GSID
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface
Benefits
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IIP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
- The MIPI RFFE Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and linux driver package
- Documentation contains User s Guide and Release notes.
Technical Specifications
Maturity
Getting used at customer site