MIPI D-PHY CSI-2 TX (Transmitter) IP in TSMC 40ULP

Overview

The MXL-DPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.5
Consists of 1 Clock lane and 4 Data lanes
Embedded, high performance, and highly programmable PLL
Supports both low-power mode and high speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
2.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support
Calibrator for resistance termination

Benefits

The MIPI D-PHY CSI-2 TX is a Mixel power and area-optimized implementation of the MIPI D-PHY supporting MIPI CSI-2 (Camera Serial Interface 2).

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 40ULP

Maturity

Available Upon Request

Availability

Upon Request

TSMC

Pre-Silicon: 40nm LP

Request Info