MIPI C/D PHY TX

Overview

This MIPI C-PHY & D-PHY combo IP is designed to compliant with the MIPI C-PHY v1.0 & D-PHY v1.2 specifications. It is designed for low power and high-performance application. The primary application is for the physical layer CSI-2 (Camera Serial Interface). Other applications that require a high data rate serial link may also benefit from the implementation of the C-PHY & D-PHY combo IP. The C-PHY & D-PHY combo IP implementation for CSI operating at a maximum high speed bit rate of 2500Mbps per each lane for D-PHY and 5700Mbps per each lane for C-PHY. The data lanes also support low power data communication operating at a maximum bit rate of 10Mbps.

Key Features

C-PHY v1.0 & D-PHY v1.2 combo compliant system interface;

Support up to 2500Mbps per each lane for D-PHY;
Support up to 5700Mbps per each lane for C-PHY
Supports 2X2lane 1X4lane configurable;
X2 ports support 1,2lanes, X4 ports support 1,2,3,4lanes;
Alternative clock lane output for DPHY X4 mode;
Support 8bit or 16bit HS data width for DPHY;
Support 16bit HS data width for CPHY;

Maximum LP data rate supported is 10 Mbps;
LP Escape mode and turnaround support;
HS de-skew/offset calibrations;

Benefits

Two PLL integrated for clock flexibility;
PHY Testability:

LP internal and external loopbacks test;
HS Internal pattern generator and checker;
IO continuity test support;

TSMC CRN22ULL Process;
Power Supply:

1.8V Power Supply for IO and analog;
0.9V core analog and digital;

Applications

Video Transmission System
Camera Sensor

Deliverables

GDSII&CDL Netlist
Verilog Model
LEF Layout Abstract(.LEF)
Liberty Timing Models(.lib)
Verify Results
Specification
Datasheet
Integration Guideline
Evaluation Plan
Leading support for package design, SI&PI modeling and production test development

Technical Specifications

Foundry, Node

TSMC 22nm

Maturity

Developing

Availability

Available

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