IPMB Verification IP

Overview

IPMB Verification IP provides an smart way to verify the IPMB two-wire bus. The SmartDV's IPMB Verification IP is fully compliant with version 1.0 and provides the following features.

IPMB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

IPMB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports IPMB specifications version 1.0.
Supports IPMB device types: Master, Slave.
Start and stop for all possible transfers.
Supports 7bit configurable Slave address.
Supports broadcast message capability.
Supports ACK/NACK mechanism.
Supports below network function mechanisms.
- Chassis request/response
- Bridge request/response
- Sensor event request/response
- Application request/response
- Firmware request/response
- Storage request/response
- OEM request/response
Supports message transaction formats.
- IPMB node-to-node transactions.
Supports out-of-Band access.
Supports non-intelligent i2c devices.
By using out-of-band access.
- Host ACK followed by device payload.
- Host NACK followed by STOP.
Built-in monitors for protocol checking, including a global bus monitor.
Functional coverage to cover all functionality of IPMB Slave and Master.
Callbacks in Master and Slave for various events.
Status counters for various events in bus.
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
IPMB Verification IP comes with complete test suite to test every feature of IPMB specification.

Benefits

Faster testbench development and more complete verification of IPMB designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the IPMB testcases to certify IPMB Master/Slave device.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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